ECE 206 Transparencies (from Alexandridis'  lectures)
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• Detailed Course Outline

1. Superscalars and ILP (Part 1,  Part 2)
2. Superscalar Microprocessors:  Survey (Part 1,  Part 2,  Part 3)
3. Superscalar and VLIWs (pdf)
4. Instruction Fetch and Decode (Part 1, Part 2)
5. Pipelining (Introduction, Operation, Advanced)
6. Instruction Issue Policies (Part 1,  Part2)
7. Hazards (Structural, Data, Control hazards)
8. Handling Data Hazards
9. Handling Control Hazards (Part 1,  Part 2)
10. Dynamic Branch Prediction:
• In Scalars
• In Superscalars
• IBM
11. Instruction-Level Parallelism
12. Multicycle & Pipelined Functional Units
13. MIPS Floating-Point Pipelines
14. Loop Unrolling & Scheduling:
• In Scalars
• In S-scalars & VLIWs
15. Hardware Scheduling
16. Register Renaming
17. Tomasulo:
• Algorithms
• Example
18. Software Scheduling in S-Sclaras: Basic Block, List
19. Reorder Buffers
20. List Scheduling
21. Trace Scheduling
22. Software Pipellining
23. Interrupts and Exception Handling
24. VLIW and EPIC
25. Multithreading - Concurrent Processors
26. Conclusions

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